Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus

ABSTRACT

The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.

CROSS-REFERENCE PARAGRAPH

The present application is a continuation of U.S. patent applicationSer. No. 15/625,085, filed Jun. 16, 2017, which is a continuationapplication of U.S. patent application Ser. No. 15/032,142, filed Apr.26, 2016, now U.S. Pat. No. 9,685,480, which is a national stage entryof PCT/JP2014/078306, filed Oct. 24, 2014, and claims the benefit ofpriority from prior Japanese Patent Application JP 2013-230271, filedNov. 6, 2013, the entire content of which is hereby incorporated byreference. Each of the above-referenced applications is herebyincorporated herein by reference in its entirety.

TECHNICAL FIELD

The present technology relates to a solid-state imaging device, a methodof manufacturing the solid-state imaging device, and an electronicapparatus, and particularly relates to a solid-state imaging device thatcan reduce the number of steps and enhance mechanical strength, a methodof manufacturing the solid-state imaging device, and an electronicapparatus.

BACKGROUND ART

There has been conventionally known a back-surface irradiation typesolid-state imaging device that receives light on the surface oppositethe surface on which a wiring layer is formed. In the solid-stateimaging device having this structure, light enters a light receivingportion without being blocked by the wiring layer, thereby enablingdrastic enhancement of sensitivity.

In recent years, there has been also proposed, as a back-surfaceirradiation type solid-state imaging device, a laminated-typecomplementary metal oxide semiconductor (CMOS) image sensor including: afirst semiconductor substrate having a pixel region; and a secondsemiconductor substrate having a logic circuit bonded to the firstsemiconductor substrate (for example, see Patent Literature 1).

CITATION LIST Patent Literature

Patent Literature 1: JP 2011-96851A

SUMMARY OF INVENTION Technical Problem

The solid-state imaging device of Patent Literature 1 includes anopening that penetrates from the first semiconductor substrate into thesecond semiconductor substrate and exposes an Al wiring formed in awiring layer of the second semiconductor substrate. The Al wiringexposed in this manner is used as an electrode pad for connecting withexterior wirings.

In such a structure, planarization by embedding of an Al wiring needs tobe sufficiently performed after the Al wiring was formed in the secondsemiconductor substrate in order to connect the first semiconductorsubstrate and the second semiconductor substrate.

However, since the Al wiring needs to have strength to bumps andbonding, the Al wiring needs to have a film thickness of 400 nm or more(preferably 500 nm or more). In this case, for sufficient planarizationby embedding of the Al wiring, an insulating film having a filmthickness that is 1.5 times the film thickness of the Al wiring needs tobe formed. Accordingly, the amount of planarization by chemicalmechanical polishing (CMP) to be performed increases. In this manner,when forming the Al wiring, instead of a Cu wiring, on the connectingsurface of the second semiconductor substrate, the number of stepstended to increase.

In addition, a low-dielectric constant film (Low-k film) is used forsuppressing the dielectric constant between wiring lines in the wiringlayer of the second semiconductor substrate. However, the Low-k film isa material having low Young's modulus. Therefore, when a layer of the Alwiring is formed on the Low-k film, the Low-k film cannot withstandmechanical stress caused by bumps and bonding, possibly causing cracks,peeling, and the like in the wiring layer.

Furthermore, the opening of the electrode pad penetrates a Si substrateof the first semiconductor substrate. When the Si substrate is broughtinto contact with the material of bumps or bonding, there has been thepossibility of an electric short between the electrode pads. To addressthis concern, an insulating spacer layer needs to be disposed near theopening in the Si substrate of the first semiconductor substrate. Thishas been also a factor of the increased number of steps.

The present technology has been achieved in view of such circumstances,and is intended to reduce the number of steps and enhance mechanicalstrength.

Solution to Problem

A solid-state imaging device according to an aspect of the presenttechnology includes: a laminate including a first semiconductorsubstrate having a pixel region and at least one second semiconductorsubstrate having a logic circuit, the at least one second semiconductorsubstrate being bonded to the first semiconductor substrate such thatthe first semiconductor substrate becomes an uppermost layer; and apenetration connecting portion that penetrates from the firstsemiconductor substrate into the second semiconductor substrate andconnects a first wiring layer formed in the first semiconductorsubstrate to a second wiring layer formed in the second semiconductorsubstrate. The first wiring layer is formed with Al or Cu.

The first semiconductor substrate can be bonded to the secondsemiconductor substrate with a back surface of the first semiconductorsubstrate upward. The first wiring layer can be embedded on the backsurface side of the first semiconductor substrate.

An opening can be further provided, the opening being formed such that atop surface of the first wiring layer is exposed. The first wiring layerincluding the exposed top surface can constitute an electrode pad.

The first wiring layer and the second wiring layer can be connectedthrough a plurality of penetration connecting portions.

The opening can be formed outside a pixel region in the firstsemiconductor substrate.

A connecting portion that connects the first wiring layer to a thirdwiring layer formed in a layer below the first wiring layer can befurther provided in the first semiconductor substrate. The connectingportion, the first wiring layer, and the penetration connecting portioncan constitute an inter-substrate wiring that electrically connects thefirst semiconductor substrate and the second semiconductor substrate.

A method of manufacturing a solid-state imaging device according to anaspect of the present technology includes the steps of: bonding a firstsemiconductor substrate having a pixel region to at least one secondsemiconductor substrate having a logic circuit such that the firstsemiconductor substrate becomes an uppermost layer; forming apenetration connecting portion that penetrates from the firstsemiconductor substrate into the second semiconductor substrate and isconnected to a second wiring layer formed in the second semiconductorsubstrate; and forming a first wiring layer with Al or Cu in the firstsemiconductor substrate, the first wiring layer being connected to thepenetration connecting portion.

An electronic apparatus according to an aspect of the present technologyincludes: a solid-state imaging device including a laminate including afirst semiconductor substrate having a pixel region and at least onesecond semiconductor substrate having a logic circuit, the at least onesecond semiconductor substrate being bonded to the first semiconductorsubstrate such that the first semiconductor substrate becomes anuppermost layer, and a penetration connecting portion that penetratesfrom the first semiconductor substrate into the second semiconductorsubstrate and connects a first wiring layer formed in the firstsemiconductor substrate to a second wiring layer formed in the secondsemiconductor substrate. The first wiring layer is formed with Al or Cu.

In an aspect of the present technology, a first semiconductor substratehaving a pixel region and at least one second semiconductor substratehaving a logic circuit are bonded together such that the firstsemiconductor substrate becomes the uppermost layer. Furthermore, afirst wiring layer formed in the first semiconductor substrate isconnected to a second wiring layer formed in the second semiconductorsubstrate through a penetration connecting portion that penetrates fromthe first semiconductor substrate into the second semiconductorsubstrate. The first wiring layer is formed with Al or Cu.

Advantageous Effects of Invention

According to an aspect of the present technology, the number of stepscan be reduced, and mechanical strength can be enhanced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating a configuration example of asolid-state imaging device according to an embodiment of the presenttechnology.

FIG. 2 is a diagram for explaining a structure of a solid-state imagingdevice.

FIG. 3 is a cross-sectional diagram illustrating a configuration exampleof a solid-state imaging device.

FIG. 4 is a flow chart for explaining manufacturing processing of asolid-state imaging device.

FIG. 5 is a flow chart for explaining manufacturing processing of asolid-state imaging device.

FIG. 6 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 7 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 8 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 9 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 10 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 11 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 12 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 13 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 14 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 15 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 16 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 17 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 18 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 19 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 20 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 21 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 22 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 23 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 24 is a diagram illustrating manufacturing steps of a solid-stateimaging device.

FIG. 25 is a cross-sectional diagram illustrating another configurationexample of a solid-state imaging device.

FIG. 26 is a cross-sectional diagram illustrating further anotherconfiguration example of a solid-state imaging device.

FIG. 27 is a block diagram illustrating a configuration example of anelectronic apparatus according to an embodiment of the presenttechnology.

DESCRIPTION OF EMBODIMENT(S)

Hereinafter, embodiments of the present technology will be describedwith reference to the drawings.

<Configuration of Solid-State Imaging Device>

FIG. 1 is a block diagram illustrating a configuration example of asolid-state imaging device according to an embodiment of the presenttechnology.

A solid-state imaging device 1 is configured as a complementary metaloxide semiconductor (CMOS) image sensor, and includes an unillustratedsemiconductor substrate (for example, a Si substrate) having a pixelregion (pixel array) 3 where a plurality of pixels 2 are regularlyarranged in a two-dimensional array state and a peripheral circuitportion.

The pixel 2 has a photoelectric conversion portion (for example, aphotodiode) and a plurality of pixel transistors (MOS transistors). Theplurality of pixel transistors may be constituted by, for example, threetransistors of a transfer transistor, a reset transistor, and anamplification transistor. Alternatively, a selection transistor may beadded so that the pixel transistors are constituted by four transistors.It is noted that an equivalent circuit of a unit pixel is similar to aknown one, and therefore detailed description thereof is omitted.

The pixel 2 may be configured as one unit pixel, or may be configured tohave a shared pixel structure. This pixel shared structure is astructure in which a plurality of photodiodes shares floating diffusionand transistors other than the transfer transistor. The peripheralcircuit portion includes a vertical drive circuit 4, a column signalprocessing circuit 5, a horizontal drive circuit 6, an output circuit 7,and a control circuit 8.

The control circuit 8 receives an input clock and a data that designatesan action mode and the like, and outputs data such as internalinformation of the solid-state imaging device 1. The control circuit 8also generates a clock signal and a control signal which serve ascriteria for the actions of the vertical drive circuit 4, the columnsignal processing circuit 5, the horizontal drive circuit 6, and thelike, based on a vertical synchronization signal, a horizontalsynchronization signal, and a master clock, and inputs these signals tothe vertical drive circuit 4, the column signal processing circuit 5,the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 is constituted by, for example, a shiftresistor, selects a pixel drive wiring, supplies the selected pixeldrive wiring with a pulse for driving a pixel, and drives pixels row byrow. That is, the vertical drive circuit 4 sequentially selects andscans the pixels 2 of the pixel region 3 row by row in the verticaldirection, and supplies the column signal processing circuit 5 with apixel signal based on a signal charge generated according to the amountof received light in the photoelectric conversion portion of each pixel2 through a vertical signal line 9.

The column signal processing circuit 5 is disposed, for example, foreach column of the pixels 2, and performs signal processing such asnoise removal to signals output from one row of the pixels 2 for eachpixel column. Specifically, the column signal processing circuit 5performs signal processing such as correlated double sampling (CDS) forremoving a specific pattern noise specific to the pixel 2, signalamplification, and analog/digital (A/D) conversion. In an output stageof the column signal processing circuit 5, a horizontal selection switch(not illustrated) is connected between the column signal processingcircuit 5 and a horizontal signal line 10.

The horizontal drive circuit 6 is constituted by, for example, a shiftresistor, sequentially outputs a horizontal scanning pulse to selecteach of the column signal processing circuits 5 in order, and outputs apixel signal from each of the column signal processing circuits 5 to thehorizontal signal line 10.

The output circuit 7 processes a signal sequentially supplied from eachof the column signal processing circuits 5 through the horizontal signalline 10, and outputs the processed signal. The output circuit 7 mayperform only buffering, or may perform black level adjustment, columnvariation correction, various types of digital signal processing, andthe like.

An input and output terminal 12 externally exchanges a signal.

<Structure of Solid-State Imaging Device>

Next, a structure of a solid-state imaging device according to thepresent technology will be described.

As a first example, a solid-state imaging device 1 a illustrated in theupper portion of FIG. 2 includes a first semiconductor substrate 21 anda second semiconductor substrate 22. The first semiconductor substrate21 has a pixel region 23 and a control circuit 24, and the secondsemiconductor substrate 22 has a logic circuit 25 containing a signalprocessing circuit. The first semiconductor substrate 21 and the secondsemiconductor substrate 22 are electrically connected with each other toconstitute the solid-state imaging device 1 a as a semiconductor chip.

As a second example, a solid-state imaging device 1 b illustrated in thelower portion of FIG. 2 includes a first semiconductor substrate 21 anda second semiconductor substrate 22. The first semiconductor substrate21 has a pixel region 23, and the second semiconductor substrate 22 hasa control circuit 24 and a logic circuit 25 containing a signalprocessing circuit. The first semiconductor substrate 21 and the secondsemiconductor substrate 22 are electrically connected with each other toconstitute the solid-state imaging device 1 b as a semiconductor chip.

<Cross-Sectional Diagram of Solid-State Imaging Device>

FIG. 3 is a cross-sectional diagram of a solid-state imaging device 1.

Although a detailed description will be provided later, the solid-stateimaging device 1 according to the present embodiment illustrated in FIG.3 is, similarly to the solid-state imaging device 1 a in FIG. 2,configured as a laminated body in which a first semiconductor wafer 31having a pixel region and a second semiconductor wafer 45 having a logiccircuit are bonded together such that the first semiconductor wafer 31becomes an upper layer.

The first semiconductor wafer 31 is bonded to the second semiconductorwafer 45 with the back surface of the first semiconductor wafer 31upward. That is, the solid-state imaging device 1 is a laminated,back-surface irradiation type solid-state imaging device.

A multilayer wiring layer 41 containing a plurality of Cu wirings 40 isformed on the frond surface side (the lower side in the drawing) of thefirst semiconductor wafer 31, and a multilayer wiring layer 55containing a plurality of Cu wirings 53 is formed on the front surfaceside (the upper side in the drawing) of the second semiconductor wafer45.

When the whole multilayer wiring layer 55 of the second semiconductorwafer 45 is formed with the Cu wirings in this manner, a connectingsurface to the first semiconductor wafer 31 can be planarized.

In the first semiconductor wafer 31 constituted by a Si substrate, Alwirings 85 and 86 are formed in such a manner as to be embedded on theback surface side (the upper side in the drawing) of the firstsemiconductor wafer 31.

When the Al wirings 85 and 86 are embedded in the first semiconductorwafer 31 constituted by a Si substrate in this manner, there can beobtained a substantially flattened pixel surface. Therefore, sweepingunevenness in applying a material of an on-chip color filter 93 or thelike can be suppressed.

It is noted that the first semiconductor wafer 31 and the Al wiring 85and 86 embedded in the first semiconductor wafer 31 are configured to beinsulated from each other by an the insulating film 84.

Furthermore, the solid-state imaging device 1 includes a plurality ofpenetration connecting portions 82, 83 a, 83 b, 83 c, and 83 d thatpenetrate from the first semiconductor wafer 31 into the secondsemiconductor wafer 45 to connect the Al wirings 85 and 86 of the firstsemiconductor wafer 31 to the Cu wirings 53 of the second semiconductorwafer 45.

In the solid-state imaging device 1, the Al wiring 85 constitutes aninter-substrate wiring that electrically connects the firstsemiconductor wafer 31 to the second semiconductor wafer 45, togetherwith the penetration connecting portion 82, and a connecting portion 81that connects the Al wiring 85 to the Cu wiring 40.

The first semiconductor wafer 31 also includes an opening 96 such thatthe top surface of the Al wiring 86 is exposed. In the solid-stateimaging device 1, the Al wiring 86 having the exposed top surfaceconstitutes an electrode pad for connecting to exterior wirings. It isnoted that the opening 96 and the Al wiring 86 are formed outside thepixel region in the first semiconductor wafer 31.

According to the above-described configuration, in comparison to theconventional structure in which an Al wiring is formed in the wiringlayer of the second semiconductor substrate, planarization by embeddingof the Al wiring does not need to be sufficiently performed. Thus, thenumber of steps can be reduced.

Furthermore, since a Si substrate, instead of a wiring layer constitutedby a Low-k film, is formed in the layer below the Al wiring in the firstsemiconductor wafer, resistance to a mechanical stress caused by bumpsand bonding increases, and mechanical strength below the electrode padcan be enhanced.

The Al wirings formed in the first semiconductor substrate are formed insuch a manner as to be embedded in the Si substrate. Since the Alwirings and the Si substrate are insulated from each other by theinsulating film, an insulating spacer layer does not need to be disposednear the opening in the Si substrate of the first semiconductorsubstrate. Thus, the number of steps can be further reduced.

<Method of Manufacturing Solid-State Imaging Device>

Next, a method of manufacturing a solid-state imaging device 1 accordingto the present embodiment will be described using FIG. 4 to FIG. 26.FIG. 4 and FIG. 5 are each a flow chart explaining the manufacturingprocessing of the solid-state imaging device 1, and FIG. 6 to FIG. 26are each a diagram explaining a manufacturing step of the solid-stateimaging device 1.

First, in step S11, a first semiconductor substrate is formed.

Specifically, as illustrated in FIG. 6, an image sensor, that is, apixel region 23 and a control circuit 24, in the state of asemi-finished product is firstly formed in a region that becomes a chipportion of a first semiconductor wafer (hereinafter, referred to as afirst semiconductor substrate) 31. In brief, a photodiode (PD) thatbecomes a photoelectric conversion portion for each pixel is formed in aregion that becomes a chip portion of the first semiconductor substrate31 constituted by a Si substrate. Furthermore, in a semiconductor wellregion 32 thereof, a source and drain region 33 for each pixeltransistor is formed. The semiconductor well region 32 is formed byintroducing a first conductive-type, for example, p-type impurities. Thesource and drain region 33 is formed by introducing a secondconductive-type, for example, n-type impurities. The photodiode (PD) andthe source and drain region 33 for each pixel transistor are formed byion implantation from the substrate surface.

The photodiode (PD) has an n-type semiconductor region 34 and a p-typesemiconductor region 35 on the substrate surface side. A gate electrode36 is formed via a gate insulating film on the substrate surfaceconstituting a pixel, and pixel transistors Tr1 and Tr2 are each formedby the gate electrode 36 and a source and drain region 33 paired withthe gate electrode 36. In FIG. 6, a plurality of pixel transistors isrepresented by two pixel transistors Tr1 and Tr2. The pixel transistorTr1 neighboring the photodiode (PD) corresponds to a transfertransistor, and a source and drain region thereof corresponds to afloating diffusion (FD). Each unit pixel 30 is isolated by an elementisolating region 38.

On the other hand, on the control circuit 24 side, a MOS transistorconstituting a control circuit is formed in the first semiconductorsubstrate 31. In FIG. 6, a MOS transistor constituting the controlcircuit 24 is represented by MOS transistors Tr3 and Tr4. The MOStransistors Tr3 and Tr4 are each formed by the n-type source and drainregion 33 and the gate electrode 36 formed via a gate insulating film.

Subsequently, a first interlayer insulating film 39 is formed on thesurface of the first semiconductor substrate 31. Then, a connecting holeis formed in the interlayer insulating film 39, and a connectionconductor 44 to be connected to a certain transistor is formed. When theconnection conductors 44 having different heights are formed, a firstinsulating thin film 43 a such as a silicon oxide film is formed on thewhole surface including the top surface of the transistor, and a secondinsulating thin film 43 b such as a silicon nitride film, which servesas an etching stopper, is laminated. On this second insulating thin film43 b, the first interlayer insulating film 39 is formed. The firstinterlayer insulating film 39 is formed by, for example, forming 10 nmto 150 nm of a P—SiO film (a plasma oxide film), and thereafter forming50 nm to 1000 nm of a non-doped silicate glass (NSG) film or aphosphosilicate glass (PSG) film. Thereafter, a dTEOS film (a siliconoxide film formed by a plasma chemical vapor deposition method (CVD)) isformed with a thickness of 100 nm to 1000 nm, and subsequently a P—SiH4film (a plasma oxide film) with a thickness of 50 nm to 200 nm isformed.

Thereafter, connecting holes having different depths are selectivelyformed in the first interlayer insulating film 39 until reaching thesecond insulating thin film 43 b that serves as an etching stopper.Subsequently, the first insulating thin film 43 a and the secondinsulating thin film 43 b both having the same film thickness in eachportion are selectively etched so as to be continuous to each connectinghole, thereby forming a connecting hole. Then, the connection conductor44 is embedded in each connecting hole.

Subsequently, multiple layers (three layers, in this example) of Cuwirings 40 are formed so as to be connected to each connection conductor44 through the interlayer insulating film 39, thereby forming amultilayer wiring layer 41. Each of the Cu wirings 40 is usually coveredby an unillustrated barrier metal layer in order to prevent Cudiffusion. The barrier metal layer is formed by forming, for example, aSiN film or a SiC film with a thickness of 10 nm to 150 nm. Furthermore,the interlayer insulating films 39 as the second and subsequent layersare formed by forming a dTEOS film with a thickness of 100 nm to 1000nm. The multilayer wiring layer 41 is formed by alternately forming theinterlayer insulating film 39 and the Cu wiring 40 formed via thebarrier metal layer. Although the multilayer wiring layer 41 is formedwith the Cu wiring 40 in the present example, it may be formed with ametal wiring made of any other metal material.

In the above-described step, there is formed the first semiconductorsubstrate 31 having the pixel region 23 and the control circuit 24 inthe state of a semi-finished product.

Returning to the flow chart of FIG. 4, a second semiconductor substrateis formed in step S12.

Specifically, as illustrated in FIG. 7, a logic circuit 25 having asignal processing circuit for processing signals in the state of asemi-finished product is formed in a region that becomes a chip portionof a second semiconductor substrate (semiconductor wafer) 45 made ofsilicon or the like. That is, a plurality of MOS transistorsconstituting the logic circuit 25 is formed in a p-type semiconductorwell region 46 on the front surface side of the second semiconductorsubstrate 45 in such a manner as to be isolated from each other byelement isolating regions 50. Here, a plurality of MOS transistors isrepresented by MOS transistors Tr6, Tr7, and Tr8. The MOS transistorsTr6, Tr7, and Tr8 are each formed by a pair of n-type source and drainregions 47 and a gate electrode 48 formed via a gate insulating film.The logic circuit 25 can be constituted by a CMOS transistor.

Subsequently, a first interlayer insulating film 49 is formed on thesurface of the second semiconductor substrate 45. Then, a connectinghole is formed in the interlayer insulating film 49, and a connectionconductor 54 to be connected to a certain transistor is formed. When theconnection conductors 54 having different heights are formed, a firstinsulating thin film 43 a such as a silicon oxide film and a secondinsulating thin film 43 b such as a silicon nitride film which serves asan etching stopper are laminated on the whole surface including the topsurface of the transistor, in a similar manner to the above description.On this second insulating thin film 43 b, the first interlayerinsulating film 49 is formed. Then, connecting holes having differentdepths are selectively formed in the first interlayer insulating film 39until reaching the second insulating thin film 43 b that serves as anetching stopper. Subsequently, the first insulating thin film 43 a andthe second insulating thin film 43 b both having the same film thicknessin each portion are selectively etched so as to be continuous to eachconnecting hole, thereby forming a connecting hole. Then, the connectionconductor 54 is embedded in each connecting hole.

Thereafter, formation of the interlayer insulating film 49 and formationof multiple layers of metal wirings are repeated, thereby to form amultilayer wiring layer 55. In the present embodiment, four layers of Cuwirings 53 are formed in a similar step to the formation step of themultilayer wiring layer 41 formed on the first semiconductor substrate31.

Then, the Cu wiring 53 is coated to form the interlayer insulating film49. The interlayer insulating film 49 on the Cu wiring 53 is formed byforming, for example, 500 nm to 2000 nm of an HDP film (high densityplasma oxide film) or a P—SiO film (plasma oxide film), and thereafterfurther forming a P—SiO film with a thickness of 100 nm to 2000 nmthereon. Thus, the multilayer wiring layer 55 including four Cu wirings53 formed via the interlayer insulating film 49 is formed.

Furthermore, on the multilayer wiring layer 55, there is formed a stresscorrection film 56 for reducing a stress caused by bonding between thefirst semiconductor substrate 31 and the second semiconductor substrate45. The stress correction film 56 is formed by forming, for example, aP—SiN film or a P—SiON film (a plasma oxide film) with a thickness of100 nm to 2000 nm.

In the above-described step, there is formed the second semiconductorsubstrate 45 having a logic circuit in the state of a semi-finishedproduct.

Returning to the flow chart of FIG. 4, in step S13, the firstsemiconductor substrate and the second semiconductor substrate arebonded together. Specifically, as illustrated in FIG. 8, the firstsemiconductor substrate 31 and the second semiconductor substrate 45 arebonded together such that the multilayer wiring layers 41 and 55 faceeach other. Bonding is, for example, performed with an adhesive agent.For connecting with an adhesive agent, an adhesive agent layer 60 isformed on one of the connecting surfaces of the first semiconductorsubstrate 31 and the second semiconductor substrate 45, so that the bothare superimposed on each other and connected through the adhesive agentlayer 60. In the present embodiment, bonding is performed such that thefirst semiconductor substrate 31 having the pixel region is disposed inthe upper layer, and the second semiconductor substrate 45 is disposedin the lower layer.

Although the first semiconductor substrate 31 and the secondsemiconductor substrate 45 are bonded together through the adhesiveagent layer 60 in the present embodiment, they may be alternativelybonded together by plasma connecting. In the case of plasma connecting,a plasma TEOS film, a plasma SiN film, a SiON film (a block film), a SiCfilm, or the like is formed on each of the connecting surfaces of thefirst semiconductor substrate 31 and the second semiconductor substrate45. The connecting surfaces on which these films have been formed aresubjected to plasma treatment and superimposed on each other, andthereafter subjected to an annealing treatment and connected to eachother. The bonding treatment is preferably performed in a lowtemperature process at 400° C. or lower that does not influence wiringsand the like.

By laminating and bonding the first semiconductor substrate 31 and thesecond semiconductor substrate 45, there is formed a laminated body 81 aincluding two different types of substrates.

In step S14, the first semiconductor substrate is reduced in thickness.

Specifically, as illustrated in FIG. 9, the first semiconductorsubstrate 31 is ground and polished from its back side so that the firstsemiconductor substrate 31 is reduced in thickness. This reduction inthickness is performed in such a manner as to border on a photodiode(PD). When, for example, a semiconductor substrate formed with a p-typehigh concentration impurity layer as an etching stopper layer (notillustrated) is used as the first semiconductor substrate 31, reductionin thickness and planarization can be achieved by removing the substrateby etching until reaching the etching stopper layer. After the reductionin thickness has been performed, a p-type semiconductor layer forsuppressing dark current is formed on the back surface of the photodiode(PD). The thickness of the first semiconductor substrate 31, which is,for example, about 750 μm, is reduced to, for example, about 2 μm to 5μm.

In a known method, such reduction in thickness is performed by bonding aseparately prepared support substrate to the multilayer wiring layer 41side of the first semiconductor substrate 31. However, in the presentembodiment, reduction in thickness of the first semiconductor substrate31 is performed by using the second semiconductor substrate 45 havingthe logic circuit 25 also as the support substrate. This back surface ofthe first semiconductor substrate 31 serves as a light incident surfacein the back-surface irradiation type solid-state imaging device.

In step S15, a reflection preventing film, an oxide film, and a nitridefilm are formed.

Specifically, as illustrated in FIG. 10, a reflection preventing film 61is formed on the back surface of the first semiconductor substrate 31.The reflection preventing film 61 is formed by forming, for example, afilm of TaO2 or HfO2 with a thickness of 5 nm to 100 nm. The reflectionpreventing film 61 made of TaO2 or HfO2 has the pinning effect at theinterface with the first semiconductor substrate 31, and this reflectionpreventing film 61 suppresses generation of dark current at theinterface with the back surface side of the first semiconductorsubstrate 31. The formed reflection preventing film 61 is subjected toan annealing treatment for dehydrating TaO2 or HfO2 constituting thereflection preventing film 61. Since the reflection preventing film 61is dehydrated by this annealing treatment, a film such as an HDP filmformed in the subsequent step can be prevented from peeling.

Thereafter, a first oxide film 62 constituted by a P—SiO film or thelike is formed with a thickness of 100 nm to 1500 nm on the reflectionpreventing film 61. Furthermore, a nitride film 63 is formed on thefirst oxide film 62, and a second oxide film 64 is formed on the nitridefilm 63.

In step S16, a pattern opening process in the Al wiring portion isperformed.

Specifically, a photoresist 71 is applied on the second oxide film 64,and subjected to patterning. Then, as illustrated in FIG. 11, an opening72 and an opening 73 of Al wirings are formed by etching. In the presentembodiment, for embedding the Al wirings in the first semiconductorsubstrate 31 constituted by a Si substrate, depth d of each of theopenings 72 and 73 needs to be defined to be a depth that is a totalamount of the thickness of an Al wiring to be embedded and the thicknessof an insulating film to be formed on the Al wiring. For example, whenthe thickness of an Al wiring is 600 nm, and the thickness of aninsulating film to be formed on the Al wiring is 200 nm, depth d of eachof the openings 72 and 73 is defined to be about 1000 nm. Here, when thethickness of the reflection preventing film 61 to the oxide film 64formed on the first semiconductor substrate 31 is 500 nm, the depth towhich the first semiconductor substrate 31 is excavated is 300 nm.

In step S17, a penetration connecting hole for forming a penetrationconnecting portion is opened.

Specifically, as illustrated in FIG. 12, a connecting hole 74 is openedby applying a photoresist 71 a and performing patterning, and thereafterperforming etching. Subsequently, as illustrated in FIG. 13, penetrationconnecting holes 75, 76 a, 76 b, 76 c, and 76 d are opened by applying aphotoresist 71 b and performing patterning, and thereafter performingetching. As a result, as illustrated in FIG. 14, the connecting hole 74and the penetration connecting hole 75 are formed in the opening 72, andthe penetration connecting holes 76 a to 76 d are formed in the opening73. The connecting hole 74 is excavated until immediately beforereaching the Cu wiring 40 formed in the first semiconductor substrate,and the penetration connecting holes 75, 76 a to 76 d are excavateduntil immediately before reaching the Cu wiring 53 formed in the secondsemiconductor substrate.

In step S18, an insulating film is formed on the opening 72 includingthe connecting hole 74 and the penetration connecting hole 75 and theopening 73 including the penetration connecting holes 76 a to 76 d, andetch back is performed. Specifically, after a SiN film or the like isformed, a TEOS film as an insulating film is formed. Accordingly, asillustrated in FIG. 15, an insulating film 80 remains on the opening 72and the side walls of the connecting hole 74 and the penetrationconnecting hole 75 as well as on the opening 73 and the side walls ofthe connecting holes 76 a to 76 d. Furthermore, the bottom of theconnecting hole 74 reaches the Cu wiring 40 formed in the firstsemiconductor substrate 31, and the bottoms of the penetrationconnecting holes 75, 76 a, 76 b, 76 c, and 76 d reach the Cu wiring 53formed in the second semiconductor substrate 45.

In step S19, metal is embedded in the connecting hole 74 and thepenetration connecting holes 75 and 76 a to 76 d.

When W is embedded as metal, an appropriate pretreatment is firstlyperformed, and then a film of high melting point metal such as Ti, TiN,Ta, and TaN is formed as an adhesion layer. Thereafter, blanket W-CVD isperformed. Furthermore, etch back is performed. Thus, as illustrated inFIG. 16, the connecting portion 81 and the penetration connectingportions 82, 83 a, 83 b, 83 c, and 83 d are formed.

It is noted that the material of the connecting portion 81 and thepenetration connecting portions 82 and 83 a to 83 d is not limited to W,and may be Cu. In this case, embedding is performed by a Cu-Seed layerand Cu plating, and then etch back on the whole surface is performed byion beam etching (IBE) or the like. Thus, the connecting portion 81 andthe penetration connecting portions 82 and 83 a to 83 d are formed.

In step S20, an insulating film is formed in the openings 72 and 73.

Specifically, as illustrated in FIG. 17, an insulating film 84 ispatterned on the side walls and the bottoms of the openings 72 and 73,such that the top surfaces of the connecting portion 81 and thepenetration connecting portions 82 and 83 a to 83 d are opened. Theinsulating film 84 has a laminated structure in which a nitride film andan oxide film, for example, are laminated to each other. As describedlater, Al wirings are to be embedded in the openings 72 and 73.Conduction between the first semiconductor substrate 31 constituted by aSi substrate and the Al wirings can be prevented by the insulating film84.

In step S21, an Al wiring material is embedded in the openings 72 and73, and patterning is performed. Accordingly, as illustrated in FIG. 18,an Al wiring 85 is formed in the opening 72, and an Al wiring 86 isformed in the opening 73.

In step S22, an oxide film is embedded.

Specifically, as illustrated in FIG. 19, an oxide film 87 is embedded inthe opening 72 in which the Al wiring 85 has been formed and in theopening 73 in which the Al wiring 86 has been formed. Here,planarization by CMP is performed to eliminate steps between portionswhere the oxide film 87 is embedded in the openings 72 and 73 and otherportions.

In step S23, a light shielding film and a planarizing film are formed.

Specifically, as illustrated in FIG. 20, a light shielding film 91 isformed on the oxide film 64 in a region other than the region in which aphotodiode (PD) is formed, and a planarizing film 92 is formed on thelight shielding film 91. The light shielding film 91 is formed with, forexample, metal such as W and Al. Alternatively, the light shielding film91 may be formed by laminating W and Ti (or Ta, TiN), or by laminatingAl and Ti (or Ta, TiN). In this case, for example, a film formed in thelower layer has a film thickness of 50 nm to 500 nm, and a film formedin the upper layer has a film thickness of 5 nm to 100 nm. Theplanarizing film 92 is applied by spin coating or the like.

In step S24, a color filter is formed.

Specifically, as illustrated in FIG. 21, an on-chip color filter 93 ofred (R), green (G), blue (B), or the like is formed on the planarizingfilm 92 in such a manner as to correspond to each pixel. The on-chipcolor filter 93 is formed above the photodiode (PD) constituting a pixelarray by forming an organic film containing a pigment or dye of eachcolor and performing patterning.

Thereafter, in step S25, a film of an on-chip lens material 94 a isformed in a pixel array region containing the area on the on-chip colorfilter 93. The on-chip lens material 94 a to be used is, for example, anorganic film or an inorganic film such as SiO, SiN and SiON, and isformed into a film with a thickness of 3000 nm to 4500 nm.

In step S27, a resist for an on-chip lens is formed.

Specifically, as illustrated in FIG. 22, a resist 95 for an on-chip lensis formed in a region corresponding to each pixel on the on-chip lensmaterial 94 a with a thickness of, for example, 300 nm to 1000 nm.

In step S28, an etching treatment is performed thereby to form anon-chip lens. Accordingly, the shape of the resist 95 for an on-chiplens is transferred to the on-chip lens material 94 a, thereby to forman on-chip lens 94 above each pixel as illustrated in FIG. 23.

Then, in step S29, an opening of an electrode pad is formed.

Specifically, there is formed a resist film having an opening on theon-chip lens 94 (the on-chip lens material 94 a) in a regioncorresponding to the Al wiring 86 in the state of FIG. 23, and etchingis performed under a predetermined etching condition until the topsurface of the Al wiring 86 is exposed. Thus, as illustrated in FIG. 24,there is formed an opening 96 in which the top surface of the Al wiring86 is exposed.

The Al wiring 86 is electrically connected to the Cu wiring 53 formed inthe second semiconductor substrate 45, through the penetrationconnecting portions 83 a to 83 d formed in such a manner as to penetratefrom the first semiconductor substrate 31 into the second semiconductorsubstrate 45.

Since the top surface of the Al wiring 86 is exposed in the opening 96,the Al wiring 86 is configured as an electrode pad for connecting withexterior wirings. It is preferable to form a plurality of the Al wirings86 configured as an electrode pad on each of three or four sides outsidethe pixel region formed in each chip.

The laminated body 81 a formed by laminating two semiconductorsubstrates is thereafter divided into chips through dicing processing.Thus, the solid-state imaging device according to the present embodimentis accomplished.

According to the above-described process, in comparison to theconventional method in which the Al wiring is formed in the wiring layerof the second semiconductor substrate, planarization by embedding of theAl wiring does not need to be sufficiently performed, and the number ofsteps can be reduced.

Furthermore, since a Si substrate, instead of a wiring layer constitutedby a Low-k film, is formed in the layer below the Al wiring in the firstsemiconductor substrate, resistance to a mechanical stress caused bybumps and bonding increases, and mechanical strength can be enhanced.

Furthermore, although the Al wiring formed in the first semiconductorsubstrate is embedded in the Si substrate, the Al wiring and the Sisubstrate are insulated from each other by the insulating film.Therefore, an insulating spacer layer does not need to be disposed nearthe opening in the Si substrate as the first semiconductor substrate,enabling the number of steps to be further reduced.

Other Configuration Examples

It is noted that although the Al wiring 86 as an electrode pad and theCu wiring 53 in the second semiconductor substrate 45 are connected viafour penetration connecting portions 83 a, 83 b, 83 c, and 83 d in theabove, the number of penetration connecting portions is not particularlylimited as long as it is two or more. For example, two penetrationconnecting portions 83 a and 83 b may be provided as illustrated in FIG.25. Alternatively, the Al wiring 86 and the Cu wiring 53 may beconnected through one penetration connecting portion.

Furthermore, although the inter-substrate wiring to electrically connectthe first semiconductor substrate 31 to the second semiconductorsubstrate 45 has a structure including the connecting portion 81, thepenetration connecting portions 82, and the Al wiring 85 in the above,other structures may be adopted.

FIG. 26 is a cross-sectional diagram illustrating a configurationexample of a back-surface irradiation type solid-state imaging deviceincluding an inter-substrate wiring having another structure.

A solid-state imaging device illustrated in FIG. 26 has a structure inwhich a first semiconductor substrate 110 having a pixel region and acontrol circuit and a second semiconductor substrate 120 having a logiccircuit are bonded together. The first semiconductor substrate 110includes a first semiconductor substrate 111 and a wiring layer 112formed on one surface (front surface) of the first semiconductorsubstrate 111. The second semiconductor substrate 120 includes a secondsemiconductor substrate 121 and a wiring layer 122 formed on the secondsemiconductor substrate 121. The first semiconductor substrate 110 andthe second semiconductor substrate 120 are bonded together such that thewiring layers 112 and 122 face each other. A connecting surface 125 isformed on the surfaces of the wiring layers 112 and 122.

The wiring layer 112 of the first semiconductor substrate 111constitutes a multilayer wiring layer including: a plurality ofconductor layers constituting a wiring, an electrode, and the like; andan interlayer insulating layer for insulating between the conductorlayers. In the example of FIG. 26, an Al wiring 116 constituted by oneof the plurality of conductor layers is illustrated in an interlayerinsulating layer 118. On the other surface (back surface) of the firstsemiconductor substrate 111, there are formed protective layers 113 and114 constituted by insulating layers. The protective layer 113 coversthe whole back surface of the first semiconductor substrate 111excluding a position where a penetration electrode 117 described lateris disposed. The protective layer 114 is disposed on the whole surfacecovering the protective layer 113 and the exposed surface of thepenetration electrode 117.

The wiring layer 122 of the second semiconductor substrate 121constitutes a multilayer wiring layer including: a plurality ofconductor layers constituting a wiring, an electrode, and the like; andan interlayer insulating layer for insulating between the conductorlayers. In the example of FIG. 26, a Cu wiring 123 constituted by one ofthe plurality of conductor layers is illustrated in an interlayerinsulating layer 124. The Al wiring 116 and the Cu wiring 123 are eachconnected with an unillustrated wiring or the like, and connected tovarious circuit elements such as a MOS transistor.

Furthermore, the solid-state imaging device illustrated in FIG. 26includes a penetration electrode 117 that penetrates from the backsurface of the first semiconductor substrate 111 through the wiringlayer 112 and the connecting surface 125 to the Cu wiring 123 of thewiring layer 122. The penetration electrode 117 is formed in an openingthat penetrates the protective layer 113, the first semiconductorsubstrate 111, and the wiring layers 112 and 122. The side surface ofthe penetration electrode 117 is connected to the inside surface of theopening of the Al wiring 116, and the bottom surface of the penetrationelectrode 117 is connected to the surface of the Cu wiring 123. In thismanner, the penetration electrode 117 as an inter-substrate wiringelectrically connects the Al wiring 116 of the wiring layer 112 and theCu wiring 123.

Furthermore, an insulating layer 115 is disposed at an interface of thefirst semiconductor substrate 111 which comes into contact with thepenetration electrode 117. The penetration electrode 117 penetrates theprotective layer 113 on the back surface of the first semiconductorsubstrate 111, and the edge surface of the penetration electrode 117 isexposed to the surface of the protective layer 113. The protective layer114 covers the top surface of this penetration electrode 117 and theprotective layer 113.

Furthermore, the insulating layer 115 is disposed at an interface of thefirst semiconductor substrate 111 which comes into contact with thepenetration electrode 117, thereby ensuring insulation between thepenetration electrode 117 and the first semiconductive substrate 11.

The present technology can also be applied to the solid-state imagingdevice having the above-described structure.

It is noted that the structure for electrically connecting the firstsemiconductor substrate and the second semiconductor substrate is notlimited to the above-described structure, and further another structuremay be provided. Furthermore, although the Al wiring made of Al is usedas the first wiring layer to be formed in the first semiconductorsubstrate in the above, a Cu wiring made of Cu or a metal wiring made ofother metal may be used.

Moreover, although the second semiconductor substrate having a logiccircuit described above is configured as a single layer, two or morelayers may be provided. That is, the present technology is alsoapplicable to a solid-state imaging device constituted by a laminateincluding three or more layers with the first semiconductor substratedisposed as the uppermost layer.

The present technology is not limited to the application to asolid-state imaging device, and is also applicable to an imaging device.Here, an imaging device refers to an electronic apparatus having animaging function, e.g., a camera system such as a digital still cameraand a digital video camera, and a mobile phone. It is noted that animaging device includes a module-like form mounted on an electronicapparatus, that is, a camera module, in some cases.

Configuration Example of Electronic Apparatus

Here, a configuration example of an electronic apparatus to which thepresent technology is applied will be described with reference to FIG.27.

An electronic apparatus 200 illustrated in FIG. 27 includes an opticallens 201, a shutter device 202, a solid-state imaging device 203, adrive circuit 204, and a signal processing circuit 205. FIG. 27illustrates an embodiment in which the above-described solid-stateimaging device 1 according to the present technology is disposed as thesolid-state imaging device 203 to an electronic apparatus (a digitalstill camera). Image light (incident light) from an imaging subjectforms an image on the imaging surface of the solid-state imaging device203 through the optical lens 201. Accordingly, signal charges areaccumulated in the solid-state imaging device 203 for a certain periodof time. The shutter device 202 controls a light illuminating period anda light shielding period to the solid-state imaging device 203.

The drive circuit 204 supplies a drive signal for controlling a signaltransfer action of the solid-state imaging device 203 and a shutteraction of the shutter device 202. The solid-state imaging device 203transfers a signal according to the drive signal (a timing signal)supplied from the drive circuit 204. The signal processing circuit 205performs various signal processing to a signal output from thesolid-state imaging device 203. A picture signal having been subjectedto signal processing is stored in a storage medium such as a memory, oris output to a monitor.

In the electronic apparatus 200 according to the present embodiment, thesolid-state imaging device 203 can achieve the reduced number of stepsand enhanced mechanical strength. As a result, there can be provided anelectronic apparatus that is inexpensive and highly reliable.

It is noted that an embodiment of the present technology is not limitedto the above-described embodiment, and various modifications arepossible within the range not departing from the gist of the presenttechnology.

Additionally, the present technology may be configured as below.

(1)

A solid-state imaging device, including:

-   -   a laminate including a first semiconductor substrate having a        pixel region and at least one second semiconductor substrate        having a logic circuit, the at least one second semiconductor        substrate being bonded to the first semiconductor substrate such        that the first semiconductor substrate becomes an uppermost        layer; and    -   a penetration connecting portion that penetrates from the first        semiconductor substrate into the second semiconductor substrate        and connects a first wiring layer formed in the first        semiconductor substrate to a second wiring layer formed in the        second semiconductor substrate,    -   wherein the first wiring layer is formed with Al or Cu.

(2)

The solid-state imaging device according to (1),

-   -   wherein the first semiconductor substrate is bonded to the        second semiconductor substrate with a back surface of the first        semiconductor substrate upward, and    -   wherein the first wiring layer is embedded on the back surface        side of the first semiconductor substrate.

(3)

The solid-state imaging device according to (2), further including:

-   -   an opening formed such that a top surface of the first wiring        layer is exposed,    -   wherein the first wiring layer including the exposed top surface        constitutes an electrode pad.

(4)

The solid-state imaging device according to (3),

-   -   wherein the first wiring layer and the second wiring layer are        connected through a plurality of penetration connecting        portions.

(5)

The solid-state imaging device according to (3) or (4),

-   -   wherein the opening is formed outside a pixel region in the        first semiconductor substrate.

(6)

The solid-state imaging device according to any of (2) to (5), furtherincluding:

-   -   a connecting portion that connects the first wiring layer to a        third wiring layer formed in a layer below the first wiring        layer in the first semiconductor substrate,    -   wherein the connecting portion, the first wiring layer, and the        penetration connecting portion constitute an inter-substrate        wiring that electrically connects the first semiconductor        substrate and the second semiconductor substrate.

(7)

A method of manufacturing a solid-state imaging device, the methodincluding the steps of:

-   -   bonding a first semiconductor substrate having a pixel region to        at least one second semiconductor substrate having a logic        circuit such that the first semiconductor substrate becomes an        uppermost layer;    -   forming a penetration connecting portion that penetrates from        the first semiconductor substrate into the second semiconductor        substrate and is connected to a second wiring layer formed in        the second semiconductor substrate; and    -   forming a first wiring layer with Al or Cu in the first        semiconductor substrate, the first wiring layer being connected        to the penetration connecting portion.

(8)

An electronic apparatus, including:

-   -   a solid-state imaging device including        -   a laminate including a first semiconductor substrate having            a pixel region and at least one second semiconductor            substrate having a logic circuit, the at least one second            semiconductor substrate being bonded to the first            semiconductor substrate such that the first semiconductor            substrate becomes an uppermost layer, and        -   a penetration connecting portion that penetrates from the            first semiconductor substrate into the second semiconductor            substrate and connects a first wiring layer formed in the            first semiconductor substrate to a second wiring layer            formed in the second semiconductor substrate,        -   wherein the first wiring layer is formed with Al or Cu.

REFERENCE SIGNS LIST

-   1 solid-state imaging device-   31 first semiconductor substrate-   40 Cu wiring-   41 multilayer wiring layer-   45 second semiconductor substrate-   53 Cu wiring-   55 multilayer wiring layer-   81 connecting portion-   82, 83 a to 83 d penetration connecting portion-   85, 86 Al wiring-   96 opening-   200 electronic apparatus-   203 solid-state imaging device

The invention claimed is:
 1. A solid-state imaging device, comprising: alaminate including a first semiconductor substrate having a pixel regionand at least one second semiconductor substrate having a logic circuit,wherein the at least one second semiconductor substrate is bonded to thefirst semiconductor substrate such that the first semiconductorsubstrate becomes an uppermost layer of the solid-state imaging device;and a penetration connecting portion that penetrates from the firstsemiconductor substrate into the at least one second semiconductorsubstrate, wherein the penetration connecting portion connects a firstwiring layer to a second wiring layer, the first wiring layer is in thefirst semiconductor substrate, the second wiring layer is in the atleast one second semiconductor substrate, the first wiring layercomprises one of Al or Cu, the first wiring layer comprises an electrodepad, and a first surface of the electrode pad is exposed through anopening and a second surface, opposite to the first surface, of theelectrode pad is in contact with the connected penetration connectingportion.
 2. The solid-state imaging device according to claim 1, whereinthe first semiconductor substrate is bonded to the at least one secondsemiconductor substrate with a back surface of the first semiconductorsubstrate upward, and the first wiring layer is embedded on the backsurface of the first semiconductor substrate.
 3. The solid-state imagingdevice according to claim 2, further comprising a connecting portionthat connects the first wiring layer to a third wiring layer, whereinthe third wiring layer is in a layer below the first wiring layer in thefirst semiconductor substrate, and the connecting portion, the firstwiring layer, and the penetration connecting portion constitute aninter-substrate wiring that electrically connects the firstsemiconductor substrate and the at least one second semiconductorsubstrate.
 4. The solid-state imaging device according to claim 1,wherein the first wiring layer and the second wiring layer are connectedthrough a plurality of penetration connecting portions, and theplurality of penetration connecting portions includes the penetrationconnecting portion.
 5. The solid-state imaging device according to claim1, wherein the opening is at outside of the pixel region in the firstsemiconductor substrate.